Mateo Valero
His research is in the area of computer architecture, with special emphasis on high performance computers: processor organization, memory hierarchy, systolic array processors, interconnection networks, numerical algorithms, compilers and performance evaluation.
Professor Valero has co-authored over 700 publications: over 500 in Conferences and the rest in Journals and book chapters. He was involved in the organization of more than 300 International Conferences as General Chair (11), including ICS95, ISCA98, ICS99 and PACT01, Steering Committee member (85), Program Chair (26) including ISCA06, Micro05, ICS07 and PACT04, Program Committee member (200), Invited Speaker (70), and Session Chair (61). He has given over 400 talks in conferences, universities and companies. He has been an associate editor of IEEE Transactions on Parallel and Distributed Systems, the IEEE Micro Journal and IEEE Computer Architecture Letters, the Journal of Parallel Programming Languages, as well as guest editing several special issues of the IEEE Transactions on Computers and Computer Magazine.