CARLA 2024

Alberto Ros Bardisa

University: University of Murcia

Country: Spain

Timely Prefetching for High Performance Computers

Prefetching instructions and data is a fundamental technique for designing high-performance computers. Timeliness is a key property to consider when designing an efficient and effective prefetcher since bringing instructions too early increases the risk of the instructions being evicted from the cache before their use and requesting them too late can lead to the instructions arriving after they are demanded. This talk elaborates on instructions and data prefetching techniques with a focus on timeliness.


Alberto Ros is full professor in the Computer Engineering Department at the University of Murcia, Spain. Funded by the Spanish government to conduct the PhD studies he received the PhD in computer science from the University of Murcia in 2009. He held postdoctoral positions at the Universitat Politècnica de València and Uppsala University. He received an European Research Council (ERC) Consolidator  Grant in 2018 to improve the performance of multicore architectures, and an ERC Proof of Concept Grant in 2024. Working on cache coherence, memory hierarchy designs, memory consistency, and processor microarchitecture, he has co-authored more than 100 peer-reviewed articles. He has been inducted into the ISCA Hall of Fame and MICRO Hall of Fame. He is IEEE Senior member.